Von der Fakultät für Maschinenbau, Elektrotechnik und Wirtschaftsingenieurwesen der Brandenburgischen Technischen Universität Cottbus zur Erlangung des akademischen Grades eines Doktor-Ingenieurs, genehmigte Dissertation, vorgelegt von
Vorsitzender: Prof. Dr.-Ing. H. Schwarz
Gutachter: Prof. Dr.-Ing. B. Falter
Gutachter: Prof. Dr. h. c. mult. U. Rhode
Gutachter: Prof. Dr.-Ing. habil. D. Engelage
Tag der mündlichen Prüfung: 03.05.2002
It is a goal of this paper to introduce and discuss a new circuit technique for the design of dual-modulus high frequency dividers with low energy consumption. The new technique is verified in a PLL frequency synthesizer loop system.
Figure 1 shows a typical example for the frequency synthesis in the 2.4 GHz range. The used PLL circuit work between 2.289 GHz and 2.369 GHz. The PLL is a central element in such a Transmitter/Receiver design.
Frequency synthesizers, used in mobile communications, spent commonly up to 90% of the total energy used for the dual-modulus RF Prescaler. Using the new circuit technique, demonstrated in this paper, a dual-modulus prescaler may reach nearly the same product of velocity and energy consumption as simple binary divider reach.
To document the limits of simple D-FF using standard CMOS circuits, chapter 3.0 give a comparison to the CML circuit technique.
To get an overview where the frequency divider is used in a frequency synthesizer, chapter 4 elucidated the functions and block circuits of the PLL circuit.
Chapter 4.5 contains a circuit technique for minimize signal deviations in PLL systems which have not been published anywhere.
Chapter 5.0 deals with architectures of frequency dividers and give an explanation about the use of dual-modulus dividers. Here are also informations about the ranges and the channel distribution of common mobile standards like DECT (eng. digital european cordless telephone) and BLUETOOTH (standard for short distance transmissions max. about 10m). Chapter 6 deals in more detail with plus and minus of some circuit techniques for RF dividers. The chapters and describe the new circuit concept for the design of energy efficient RF dividers. These dividers have been verified using the experimental circuit described in chapter 7.0. There is also a comparison to other designs which have been found in the literature. At the end of this chapter a trend evaluation of the required power consumption versus the used technology is published.
A short summary of the CMOS experiment, the influence on state of the art and some opportunities for the further work are included in chapter 8.0.
Appendix A is a design study for a complete frequency synthesizer using the new presented circuit technique, incl. the used CADENCE schematics as well as some signal charts from the simulations. This PLL test circuits do not include programmable divers required for channel selection. But the low frequency programmable dividers do not influence the total energy consumption too much (<5%).