BLUETOOTH transceiver / RF CMOS Circuits

homepage
of
Michael Dietmar Pierschel

Design of the required low speed counters [LSC]

frequency divider architecture

The counters P and S each consist actually of cascaded 4 Bit synchron counters incl. latches. The required decision logic is different for P and S counter to meet the timing conditions for a prescaler mode switching up to about 200 MHz operating frequency (see circuit schematics (not online available) for details).

technical specifications

supply voltage	3V (+0V, -0.3V)
ambient temperature	0 degree C to 120 degree C
input frequency	up to 200 MHz
input level	0/3V digital CMOS signals
output level	0/3V digital CMOS

A short documentation of the MOSIS Oct. 1999 run tapeout data is available in oct99run.htm. Kontakt: mailto: Hier klicken !