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Michael Dietmar Pierschel


CMOS prescaler basics

Short CML Divider Technology Test

High Speed Binary Divider Architectures

Conventional Type

CMOS Stacked Flip-Flop Type

Full CMOS Crossed Flip-Flop Type

Dual Modulus Prescaler Architectures

Common Dual Modulus Divider Architectures

Shift Register Architectures

Hard Redundance Architecture

Cycle Stealing Architecture

Power Save Techniques

Next Steps

Technology Tests

the frequency range up to 2.5 GHz can be adressed with 250 nm CMOS

With reduced parasitics 60 fF instead of 100 fF per switching node

signals up to 3 GHz have been processed correct in the simulation.

the power requirements fall below 1 mW per FF

( without current save techniques )

the delay time of 250 nm p- and n-channel transistors are nearlythe same

check the model accuracy in the 1...3 GHz range

check if ballistic charge transport becomes dominant in the 250 nm

channel length region

enhanced drift fields in the p-channel transistors due tu a burriedchannel technology

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Standard CML Flip-Flop's

Conventional Type

Stacked Flip-Flop's

HCrossed Flip-Flop's

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Common Dual Modulus Divider Architectures

Common Dual Modulus Divider Architectures

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Synchron Johnson Counter's

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Shift Register Architectures

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Power Save Technique

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New Prescaler Architectures

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modified D-FF

cycle stealing method

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Proposed Architecture

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new prescaler layout

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Designed Prescaler Circuits

prescaler performance summary

technologyfrequencypowercomments
CMOS

0.25 m m

9.5 G8 mW@2.5Vdiv128/129 cycle stealing method, power down
CMOS

0.25 m m

7.5 G18 mW@2.5Vdiv128/129 standard, power down

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Opportunities for low power operation

bit synchron current switching

high speed FF power down

FF stacking / curren reuse at low speed

logic power down options ( hard redundance architecture )

output driver power control circuit

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Next Steps

verify MOS models @ 1 ... 3 GHz by measurement

investigation of new architectures

optimize input driver

optimize init / control logic / div32

introduce current save techniques to the ring structure

layout generation / parasitic extract / parasitic simulation

implementation of standby mode

investigations to dynamic prescaler opportunities

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